1. Field of the Invention
The present invention relates to the field of integrated circuits.
2. Discussion of the Related Art
The fast development of technology has led to an increase in circuit complexity at the same time as a decrease in the commercial lifetime of circuits. Conversely, the time required by a manufacturing cycle (mask patterning, processing of the silicon wafers, circuit testing and encapsulating) remains significant.
Inevitably, after designing a complex integrated circuit, the first manufactured circuits frequently exhibit errors. The circuit can then be run back through the design steps to attempt to correct the error, prior to starting again a manufacturing batch. This requires a new thorough cycle of manufacturing, which is costly and long and can put the commercial interest of the circuit at risk.
It is thus often preferred to correct the hardware element formed by the integrated circuit itself. This, with the purpose of validating the correction on a few prototypes only. The correction on circuits produced in series can only be done by modifying the masks. An integrated circuit generally includes a semiconductor substrate currently made of silicon in which the several primary circuit components are formed. This substrate is topped by several levels of conductive layers (polysilicon, metallizations, generally called "metallization levels"). Once a defect has been identified in the integrated circuit, such as a missing logic function, high precision machines (MDL 1000 of Bertin/Spectra Physics for the laser cut, FIB (Focus Ion Beam) of Schlumberger for the cut and the perforation, the metal deposition and the oxide deposition) are used to perforate the metallization levels to obtain access to the terminals of the primary components, to disconnect these components and to connect back the inputs and the outputs of these components to a "standby cell" in order to add the missing logic function.
Standby cells have no function in the circuit as long as this circuit does not require correction, and their inputs are conventionally grounded to avoid useless power consumption. Standby cells are conventionally implanted by groups. FIG. 1A schematically shows a conventional group 11 of standby cells formed of a NAND gate (1), of a D flip-flop (2) and of a tri-state gate (3) that enable a great variety of corrections.
FIG. 1B shows as an example a very simplified top view of an integrated circuit, the basic components of which have not been shown. In this integrated circuit 10, a great number of groups of standby cells 11 is implanted. These cells, in a repair, are to be connected to selected circuit nodes. These cells must be very numerous since a limitation of the above-mentioned correction method is that machines for establishing the replacement connections (conventionally by implantation of metal at the circuit surface) do not allow, for technical reasons, replacement connections to exceed a given length (.DELTA.). For a circuit to be possibly repaired at each of its nodes, each of its nodes must not be further than length .DELTA. from a group of standby cells. Thus, standby cell groups 11 are conventionally arranged according to rows and columns distant by 2.DELTA./2 from one another across the entire circuit 10 that is desired to be made repairable. Also, the groups of cells can be at a distance of .DELTA./2 from the edges of the circuit that is desired to be made repairable. The standby cells, implanted among the basic circuit components, occupy a surface which is far from being negligible and increase the circuit surface, and thereby its cost.
Taking as an example a circuit such as shown in FIG. 1B, of 10 mm.times.10 mm, .DELTA. being equal to 400 .mu.m, the number of implanted standby cell groups will be (10,000.times.2/400).times.(10,000.times.2/400)=10,000/8=1,250. Assuming that a group of standby cells is formed of approximately forty transistors, the groups of standby cells in this embodiment according to prior art altogether amount to 1,250.times.40=50,000 transistors. A chip of 10 mm.times.10 mm conventionally amounts to one million transistors, and the standby cells represent in this case 5% of the chip surface, which will increase the chip price by at least 5%.
To maintain reasonable prices, there is a temptation to reduce the number of standby cell groups, and to place them only in the circuit areas which are the most likely to exhibit errors, but the insurance of being able to perform a repair at any node of the circuit is thereby lost, and problems of impossible repairs sometimes arise.
Another limitation of this method is associated with the fact that the cutting or the establishing of a connection leads to digging the upper surfaces of the circuit to the connection to be cut, and to the terminals of the standby cell which is desired to be connected. The deeper the elements to be reached, the more the subsequent digging operation and connection operation will be delicate, long and costly.